B. Li, Luo, Z. Q., Shi, L., Zhou, J. P., Rabenberg, L. K., Ho, P. S., Allen, R. A., and Cresswell, M. W., “Controlled Formation and Resistivity Scaling of Nickel Silicide Nanolines,” Nanotechnology 20, vol. 20, pp. 085304, 2009.
We demonstrate a top-down method for fabricating nickel mono-silicide (NiSi) nanolines (also referred to as nanowires) with smooth sidewalls and line widths down to 15 nm. Four-probe electrical measurements reveal that the room temperature electrical resistivity of the NiSi nanolines remains constant as the line widths are reduced to 23 nm. The resistivity at cryogenic temperatures is found to increase with decreasing line width. This finding can be attributed to electron scattering at the sidewalls and is used to deduce an electron mean free path of 6.3 nm for NiSi at room temperature. The results suggest that NiSi nanolines with smooth sidewalls are able to meet the requirements for implementation at the 22 nm technology node without degradation of device performance.